The subject matter of the present invention relates generally to the manufacture of integrated circuits, and in particular to a method of manufacture of a CMOS integrated circuit including a plurality of complementary insulated gate field effect transistors, and to the integrated circuit produced thereby. The method of manufacture of the present invention is especially useful to make high-speed and high-density integrated circuits having a frequency response of up to 400 megahertz and a density of up to 500,000 transistors per square centimeter. The resulting device is very large scale integration (VLSI) integrated circuit of high-speed.
It has been previously proposed in U.S. Pat. No. 4,356,211 of Riseman issued Oct. 26, 1982 to provide an integrated circuit of bipolar PN junction transistors with a dielectric isolation region of silicon dioxide formed in deep trenches. The trenches are etched by reactive ion etching through an epitaxial layer provided on the semiconductor substrate and contain oxidized polycrystalline silicon within the trench. Polycrystalline silicon is provided as two horizontally spaced layers on the opposite vertical sides of the trench. The vertical layers of polycrystalline silicon are thermally oxidized and caused to grow together across the width of the trench until they join at the top of the trench, thereby forming an air space within the polycrystalline silicon oxide filling of the dielectric isolation region. Thus, the top portion of the vertical layer of polycrystalline silicon on the wall of the trench is doped with an impurity so that it will oxidize at a faster rate than the lower portion of such vertical layer. As a result, the top portions grow together first to form a cap of silicon dioxide which seals the upper end of the trench before the lower portions of the vertical layer have grown together, thereby leaving a cavity or air space within the filling of polycrystalline silicon oxide forming the dielectric isolation region. This air space and silicon oxide isolation region causes defective operation of transistors especially when used in MOS insulated gate field effect transistor integrated circuits.
In addition, it has been found that by providing the dielectric isolation region of a CMOS integrated circuit in the manner of the present invention with filling of unoxidized polycrystalline silicon over a silicon dioxide layer coated on the entire inner surface of the trench, such isolation region has a thermal coefficient of expansion which more closely matches the silicon of the semiconductor substrate. This reduces thermal stress which tends to cause leakage currents at the edges of the PN junction which are adjacent the isolation region and also prevents positive feedback "latch-up" operation of the transistor. Thus, the method of manufacture of the present invention eliminates the air space and thermal stress problems of the Riseman patent.
It has been previously proposed by T. Shibata, et al in the article "An Optimumly Designed Process for Submicron MOSFETS", pages 647-650 of the IEEE Proceedings of the International Electron Device Meeting (IEDM) 1981, and by P. A. Gargini, et al in the article "WOS: Low Resistance Self-Aligned Source, Drain and Gate Transistors", pages 54-57 of the IEEE Proceedings of the International Electron Device Meeting (IEDM) 1981, to manufacture CMOS transistors having refractory metal silicide areas provided on the source, drain and gate elements of the transistor to lower the ohmic contact resistance and the interconnect resistance of such elements. However, in the Shibata article, the refractory metal employed to form the silicide areas is platinum which is of too high resistivity and is too expensive. In the Gargini article, the tungsten used as the refractory metal to form the silicide is also of relative high resistivity. In addition, Gargini uses chemical vapor deposition to deposit the tungsten on the silicon at sufficiently high temperatures to form tungsten silicide simultaneously with the deposition of the tungsten. However, this has the disadvantage that the tungsten is deposited with a non-uniform thickness so that the tungsten silicide coating is not reproducible in production integrated circuits.
In order to overcome these problems, the method of manufacture of the present invention employs a process employing titanium or tantalum as the refractory metal which forms the refractory metal silicide with the silicon of the source and drain and with the polysilicon of the gate. Titanium and tantalum have the advantage that they have a much lower sheet resistance on the order of 2 to 3 ohms per square, which is less than half the 5 to 8 ohms per square sheet resistance of platinum and tungsten. However, titanium and tantalum have the disadvantage that they readily form an oxide which is very difficult to remove by etching as is required for those refractory metal portions on the silicon dioxide layer which do not form a silicide. This oxidation problem is overcome in the present invention by using a double layer of two different refractory metals including an outer layer of a refractory metal such as molybdenum which does not readily oxidize during silicidation as a protective layer over the inner layer of titanium or tantalum to prevent oxidation of such inner layer. This has the advantage that the portions of the refractory metal inner layer which do not form a silicide and the entire outer layer can be selectively removed by etching refractory metal silicide on the source, drain and gate elements of the MOS field effect transistor. Siliciding is performed in two steps including a first silicidation at low temperature of about 600.degree. C. to prevent the silicon dioxide layer from forming a silicide with the inner layer of refractory metal. After selectively etching to remove the refractory metal on the silicon dioxide layer of the insulated gate which does not form a silicide, the device is again heated but to a higher temperature of about 800.degree. C. for further silicidation on the source, drain and gate elements to reduce the sheet resistance to approximately 2 to 3 ohms per square.
Another advantage of the method of manufacture of the present invention is the prevention of the formation of a "bird's beak" portion of greater thickness in the silicon dioxide insulation layer of the insulated gate field effect transistor. Bird's beak formation is the result of lateral diffusion of the oxygen atoms during thermal growth of the silicon dioxide isolation regions surrounding the field effect transistors and reduces the density of transistors formed in the integrated circuit. Such a bird's beak, also, reduces the effective width of the channel portion of the field effect transistor and, therefore, deleteriously effects its performance. Bird's beak formation is prevented by providing a silicon nitride side wall cover layer extending over the vertically sides at the opposite ends of the silicon oxide insulating layer forming the insulated gate. The silicon nitride side wall prevents lateral diffusion of the oxygen atoms of such insulating layer, thereby stopping the growth of any bird's beak portion. The silicon nitride side walls are joined to a silicon nitride top layer over the upper surface of the silicon dioxide insulating layer to form a protective "nitride cup" which prevents any increase in thickness of the gate insulating layer during subsequent heat treatment.